Semiconductor wafers are generally prepared from a single crystal ingot (e.g., a silicon ingot) which is trimmed and ground to have one or more flats or notches for proper orientation of the wafer in subsequent procedures. The ingot is then sliced into individual wafers. While reference will be made herein to semiconductor wafers constructed from silicon, other materials may be used to prepare semiconductor wafers, such as germanium, silicon carbide, silicon germanium, gallium arsenide, and other alloys of Group III and Group V elements, such as gallium nitride or indium phosphide, or alloys of Group II and Group VI elements, such as cadmium sulfide or zinc oxide.
Semiconductor wafers (e.g., silicon wafers) may be utilized in the preparation of composite layer structures. A composite layer structure (e.g., a semiconductor-on-insulator, and more specifically, a silicon-on-insulator (SOI) structure) generally comprises a handle wafer or layer, a device layer, and an insulating (i.e., dielectric) film (typically an oxide layer) between the handle layer and the device layer. Generally, the device layer is between 0.01 and 20 micrometers thick, such as between 0.05 and 20 micrometers thick. Thick film device layers may have a device layer thickness between about 1.5 micrometers and about 20 micrometers. Thin film device layers may have a thickness between about 0.01 micrometer and about 0.20 micrometer. In general, composite layer structures, such as silicon-on-insulator (SOI), silicon-on-sapphire (SOS), and silicon-on-quartz, are produced by placing two wafers in intimate contact, thereby initiating bonding by van der Waal's forces, followed by a thermal treatment to strengthen the bond. The anneal may convert the terminal silanol groups to siloxane bonds between the two interfaces, thereby strengthening the bond.
After thermal anneal, the bonded structure undergoes further processing to remove a substantial portion of the donor wafer to achieve layer transfer. For example, wafer thinning techniques, e.g., etching or grinding, may be used, often referred to as back etch SOI (i.e., BESOI), wherein a silicon wafer is bound to the handle wafer and then slowly etched away until only a thin layer of silicon on the handle wafer remains. See, e.g., U.S. Pat. No. 5,189,500, the disclosure of which is incorporated herein by reference as if set forth in its entirety. This method is time-consuming and costly, wastes one of the substrates and generally does not have suitable thickness uniformity for layers thinner than a few microns.
Another common method of achieving layer transfer utilizes a hydrogen implant followed by thermally induced layer splitting. Particles (atoms or ionized atoms, e.g., hydrogen atoms or a combination of hydrogen and helium atoms) are implanted at a specified depth beneath the front surface of the donor wafer. The implanted particles form a cleave plane in the donor wafer at the specified depth at which they were implanted. The surface of the donor wafer is cleaned to remove organic compounds or other contaminants, such as boron compounds, deposited on the wafer during the implantation process.
The front surface of the donor wafer is then bonded to a handle wafer to form a bonded wafer through a hydrophilic bonding process. Prior to bonding, the donor wafer and/or handle wafer are activated by exposing the surfaces of the wafers to plasma containing, for example, oxygen or nitrogen. Exposure to the plasma modifies the structure of the surfaces in a process often referred to as surface activation, which activation process renders the surfaces of one or both of the donor water and handle wafer hydrophilic. The surfaces of the wafers can be additionally chemically activated by a wet treatment, such as an SC1 clean or hydrofluoric acid. The wet treatment and the plasma activation may occur in either order, or the wafers may be subjected to only one treatment. The wafers are then pressed together, and a bond is formed there between. This bond is relatively weak, due to van der Waal's forces, and must be strengthened before further processing can occur.
In some processes, the hydrophilic bond between the donor wafer and handle wafer (i.e., a bonded wafer) is strengthened by heating or annealing the bonded wafer pair. In some processes, wafer bonding may occur at low temperatures, such as between approximately 300° C. and 500° C. The elevated temperatures cause the formation of covalent bonds between the adjoining surfaces of the donor wafer and the handle wafer, thus solidifying the bond between the donor wafer and the handle wafer. Concurrently with the heating or annealing of the bonded wafer, the particles earlier implanted in the donor wafer weaken the cleave plane.
A portion of the donor wafer is then separated (i.e., cleaved) along the cleave plane from the bonded wafer to form the SOI wafer. Cleaving may be carried out by placing the bonded wafer in a fixture in which mechanical force is applied perpendicular to the opposing sides of the bonded wafer in order to pull a portion of the donor wafer apart from the bonded wafer. According to some methods, suction cups are utilized to apply the mechanical force. The separation of the portion of the donor wafer is initiated by applying a mechanical wedge at the edge of the bonded wafer at the cleave plane in order to initiate propagation of a crack along the cleave plane. The mechanical force applied by the suction cups then pulls the portion of the donor wafer from the bonded wafer, thus forming an SOI wafer.
According to other methods, the bonded pair may instead be subjected to an elevated temperature over a period of time to separate the portion of the donor wafer from the bonded wafer. Exposure to the elevated temperature causes initiation and propagation of cracks along the cleave plane, thus separating a portion of the donor wafer. The crack forms due to the formation of voids from the implanted ions, which grow by Ostwald ripening. The voids are filled with hydrogen and helium. The voids become platelets. The pressurized gases in the platelets propagate micro-cavities and micro-cracks, which weaken the silicon on the implant plane. If the anneal is stopped at the proper time, the weakened bonded wafer may be cleaved by a mechanical process. However, if the thermal treatment is continued for a longer duration and/or at a higher temperature, the micro-crack propagation reaches the level where all cracks merge along the cleave plane, thus separating a portion of the donor wafer. This method allows for better uniformity of the transferred layer and allows recycle of the donor wafer, but typically requires heating the implanted and bonded pair to temperatures approaching 500° C.
Ultra-thin silicon-on-insulator (UTSOI) substrates have been used as the platform for low power high-performance complementary metal-oxide-semiconductor (CMOS) devices. See S. Deleonibus, et. al., “Future Challenges and Opportunities for Heterogeneous Process Technology, Towards the Thin Films, Zero Intrinsic Variability Devices, Zero Power Era,” in IEDM, San Francisco, 2014. UTSOI provide significant advantages compared to bulk silicon CMOS technology. For details, see Q. Liu, “FDSOI CMOS Devices Featuring Dual Strained Channel and Thin BOX Extendable to the 10 nm Node,” in IEDM, San Francisco, 2014. These advantages of UTSOI include: 1) the fully depleted channel provides immunity to short channel effect; 2) the ultra-thin Si body isolated by the thin BOX (25 nm) forms natural shallow junctions and minimizes the junction capacitance; and 3) the thin BOX enhances electrostatic control through back gate bias from the substrate. Despite the advantages, the performance of devices built on UTSOI is still limited by the Si carrier mobility. High-mobility channel materials, like SiGe, provide an additional device performance booster. See G. Hellings, et. al., “Implant-Free SiGe Quantum Well pFET: A novel, highly scalable and low thermal budget device, featuring raised source/drain and high-mobility channel,” in IEDM, San Francisco, 2010; and S. Krishnan, “A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications,” in IEDM, Washington D.C., 2011. To extend the benefit of UTSOI, ultra-thin SiGe-on-Insulator (UTSGOI) substrates are of great interest. However, unlike the cheap and readily available silicon wafers, silicon germanium is conventionally epitaxially grown on silicon substrates. The lattice mismatch between silicon germanium and silicon leads to high threading dislocation densities (>108 cm−2) and rough surface (Rms>2 nm). See M. L. Lee, “Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol. 97, p. 011101, 2005. SGOI is usually obtained by smart-cut technology and the transferred silicon germanium layer has the same defect density as an epitaxially prepared silicon germanium layer. See Z. Y. CHeng, “SiGe-On-Insulator (SGOI): substrate preparation and MOSFET fabrication for electron mobility evaluation,” in SOI Conf., Durango, Colo., USA, 2001. In addition, the transferred silicon germanium layer needs additional processing to achieve the required thickness and to smooth the surface. Layer thinning is normally done by chemical mechanical polishing (CMP) that utilizes both mechanical polishing and chemical etching. See Z. Cheng, et. al., “Electron Mobility Enhancement in Strained-Si n-MOSFETs Fabricated on SiGe-on-Insulator (SGOI) Substrates,” IEEE Elect. Dev. Lett., vol. 22, no. 7, p. 321, 2001. Silicon germanium is much more susceptible to chemicals commonly used in silicon wafer manufacture, so that processing silicon germanium is more challenging, especially when controlling the thickness of layer on the order of angstroms.